Simultaneous Place and Route for Wire-Constrained FPGAs

Simulated annealing placement algorithms which use minimumwire length metrics based on rectilinear approximations fail to accurately account for an FPGA's routing resources since the number of logic block interconnections could be limited, causing certain placements to rely on resources which may not exist. In this paper we present a simulated annealing-based placement algorithm which performs a simple but e ective route after each swap. We will show that, on wire-constrained FPGAs, our algorithm is a better evaluator for a given placement than the faster wire length metrics. In particular, on the Triptych 3-input RLB 4 16 array the algorithm achieves nal delays ranging from 3.5% to 21.5% faster than delays yielded by a cost function tailored for the architecture. In addition, the algorithm demonstrates its adaptability by producing even better results on the most recent variant of the Triptych architecture. Finally, we will show that our method can be implemented without an unreasonable increase in execution time.